Oscillators are useful system components in digital and analog systems that require clock signals. A digital oscillator can be used to generate a clock signal with an accumulating register arrangement. At a predetermined clock rate, a value stored in a register of the digital oscillator is increased in value by a control value that is successively applied to an input of the digital oscillator. The digital oscillator periodically overflows, but continues to accumulate over successive iterations of the accumulation of the control value. The average rate of the overflow of the digital oscillator is dependent upon the control value selected and the bit resolution of the register in the digital oscillator.
In one example, the most significant bit of a 4-bit register in the digital oscillator is representative of the output clock signal. The 4-bit register can accommodate storing values in the range from 0 through 15 in binary increments. The most significant bit of the register corresponds to logic 0 for register values between 0 and 7, and logic 1 for register values that are between 8 and 15. The period of the output clock signal is determined by the control values. For a control value of 2, the digital oscillator will accumulate values corresponding to 0, 2, 4, 6, 8, 10, 12, and 14 followed by an attempt to accumulate a value of 16. Since the value of 16 exceeds the capabilities of the 4-bit register, the 4-bit register will overflow to zero. For the above-described sequence, the most significant bit of the register has a duty cycle of exactly 50% with a frequency that is exactly half of the frequency of the input system clock signal.
In another 4-bit register example, a control value of 3 is applied to the digital oscillator so that, the digital oscillator will accumulate values corresponding to 0, 3, 6, 9, 12 and 15 followed by an attempt to accumulate a value of 18. Since the value of 18 exceeds the capabilities of the 4-bit register, the 4-bit register will overflow to a value of 2. The accumulation continues as: 2, 5, 8, 11, 14 and an attempt to accumulate a value of 17, resulting in an overflow to a value of 1. Accumulation again continues as: 1, 4, 7, 10, and 13, with an attempt to accumulate a value of 16, which overflows to a value of 0. The complete repeating sequence of accumulations is thus given as: 0, 3, 6, 9, 12, 15, 2, 5, 8, 11, 14, 1, 4, 7, 10 and 13 and therefore covers all sixteen possible states of the four bit register. The most significant bit for this repeating sequence corresponds to: 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, etc. For the above-described sequence, the most significant bit of the register is logic 0 exactly 50% of the time and the frequency of the output clock signal is on average one third of the frequency of the input system clock.